View ICE3DS01L05_4748613.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

pwm-ff ic ice3ds01l ice3ds01lg off-line smps current mode controller with integrated 500v startup cell never stop thinking. power management & supply datasheet, version 2.1, 15 nov 2005
edition 2005-11-15 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen ? infineon technologies ag 1999. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon tech- nologies office in germany or our infineon technol ogies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-sup port devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intend ed to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is rea - sonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com coolmos?, coolset? are trademarks of infineon technologies ag. ice3ds01l(g) revision history: 2005-11-15 datasheet previous version: 2.0 page subjects (major changes since last revision) update to pb-free package
type f osc package ice3ds01l 110khz pg-dip-8-6 ice3ds01lg 110khz pg-dso-8-8 version 2.1 3 15 nov 2005 f3 ice3ds01l ice3ds01lg c softs c vcc c bulk converter dc output + ice3ds01/g snubber power management pwm controller current mode 85 ... 270 vac typical application r sense gate cs startup cell hv precise low tolerance peak current limitation softs fb gnd vcc active burst mode latched off mode auto restart mode control unit - off-line smps current mode controller with integrated 500v startup cell p-dso-8-3, -6 test pg-dip-8-6 pg-dso-8-8 product highlights ? active burst mode to rea ch the lowest standby power requirements < 100mw ? latched off mode to increase robustness and safety of the system ? adjustable blanking wi ndow for high load jumps to increase reliability ? pb-free plating and rohs compilance features ? active burst mode for lowest standby power @ light load controlled by feedback signal ? fast load jump response in active burst mode ? 500v startup cell switched off after start up ? 110khz internally fixed switching frequency ? latched off mode for overtemperature detection ? latched off mode for overvoltage detection ? latched off mode for short winding detection ? auto restart mode for overload and open loop ? auto restart mode for vcc undervoltage ? user defined soft start ? minimum of external components required ? max duty cycle 72% ? overall tolerance of current limiting < 5% ? internal leading edge blanking ? soft driving for low emi description the f3 controller provides ac tive burst mode to reach the lowest standby power requirements <100mw at no load. as during active burst mode the co ntroller is always active there is an immediate response on load jumps possible without any black out in the smps. in active burst mode the ripple of the output voltage can be reduced <1%. furthermore latched off mode is entered in case of overtemperature, overvoltage or short winding. if latched off mode is entered only the disconnection from the main line can reset the controller. auto restart mode is entered in case of failure modes like open loop or overload. by means of the internal precise peak current limitation the dimension of th e transformer and the secondary diode can be lower which leads to more cost efficiency. an adjustable blanking window prevents the ic from entering auto restart mode or active burst mode in case of high load jumps.
f3 ice3ds01l/lg table of contents page version 2.1 4 15 nov 2005 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 pin configuration with pg-dip-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin configuration with pg-dso-8-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 representative blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 3.4.2 pwm-latch ff1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4.3 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5.1 leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5.2 propagation delay compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3.6.1 adjustable blanking wi ndow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6.2 active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.2.1 entering active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.2.2 working in active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.2.3 leaving active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.3 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.3.1 latched off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.3.2 auto restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.4 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.5 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.6 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
version 2.1 5 15 nov 2005 f3 ice3ds01l/lg pin configuration and functionality 1 pin configuration and functionality 1.1 pin configuration with pg-dip-8-6 figure 1 pin configuration pg-dip-8-6(top view) note: pin 4 and 5 are shorted within the dip package. 1.2 pin configuration with pg-dso-8-8 figure 2 pin configuration pg-dso-8-8(top view) pin symbol function 1 softs soft-start 2 fb feedback 3 cs current sense 4 hv high voltage input 5 hv high voltage input 6 gate driver stage output 7 vcc controller supply voltage 8 gnd controller ground package pg-dip-8-6 1 6 7 8 4 3 2 5 gnd softs fb cs vcc gate hv hv pin symbol function 1 softs soft-start 2 fb feedback 3 cs current sense 4 gate driver stage output 5 hv high voltage input 6 n.c. not connected 7 vcc controller supply voltage 8 gnd controller ground package pg-dso-8-8 1 6 7 8 4 3 2 5 gnd softs fb cs vcc n.c. gate hv
version 2.1 6 15 nov 2005 f3 ice3ds01l/lg pin configuration and functionality 1.3 pin functionality softs (soft start & auto restart control) the softs pin combines the function of soft start in case of start up and auto restart mode and the controlling of the auto restart mode in case of error detection. furthermore the blanking window for high load jumps is adjusted by means of the external capacitor connected to softs. fb (feedback) the information about the regu lation is provided by the fb pin to the internal protection unit and to the internal pwm- comparator to control the duty cycle. the fb-signal controls in case of light load the active burst mode of the controller. cs (current sense) the current sense pin senses the voltage developed on the series resistor inserted in the source of the external powermos. if cs reaches the internal threshold of the current limit comparator, the driver output is immediately switched off. fu rthermore the curre nt information is provided for the pwm-compar ator to realize the current mode. gate the gate pin is the output of the internal driver stage connected to the gate of an external powermos. hv (high voltage) the hv pin is connected to th e rectified dc input voltage. it is the input for the integrated 500v startup cell. vcc (power supply) the vcc pin is the positive supply of the ic. the operating range is between 8.5v and 21v. gnd (ground) the gnd pin is the ground of the controller.
f3 ice3ds01l/lg representative blockdiagram version 2.1 7 15 nov 2005 internal bias voltage reference oscillator duty cycle max c11 x3.7 soft-start comparator current limiting pwm op current mode soft start c2 c1 21v 4.0v r fb power management c softs c vcc 85 ... 270 vac c bulk + converter dc output v out ice3ds01l/lg snubber spike blanking 8.0us pwm comparator c3 5.4v c4 4.8v r softs gate driver 0.72 clock r sense gate 0.85v c9 0.3v 10k ? d1 t2 c6 1.32v c5 4.0v c10 1.66v r s q vcc active burst mode auto restart mode & g7 & g5 & g9 1 g8 & g1 1 g3 thermal shutdown t j >140c 3.25k ? 4.4v s1 6.5v & g4 1 t1 power-down reset latched off mode reset v vcc < 6v latched off mode cs softs gnd vcc c7 c8 fb pwm section control unit ff1 t3 c12 & 0.257v leading edge blanking 220ns 5k ? 10pf 6.5v g10 spike blanking 190 ns 1v 5k ? 1pf propagation-delay compensation 6.5v undervoltage lockout 15v 8.5v v csth hv vcc startup cell & g6 g1 1 g2 & - 2 representative blockdiagram figure 3 representative blockdiagram
version 2.1 8 15 nov 2005 f3 ice3ds01l/lg functional description 3 functional description all values which are used in the functional description are typical values. for calculating the worst cases the min/max values which can be found in section 4 electrical characteristics have to be considered. 3.1 introduction the f3 is the further development of the f2 to meet the requirements for the lowest standby power at minimum load and no load conditions. a new fully integrated standby power concept is implemented in to the ic in order to keep the application design easy. compared to f2 no further external parts are needed to achieve the lowest standby power. an intelligent active burst mode is used for this standby mode. after entering th is mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal pwm control. the response on load jumps is optimized. the voltage ripple on v out is minimized. v out is further on well controlled in this mode. the usually external connected rc-filter in the feedback line after the optocoupler is integrated in the ic to reduce the external part count. furthermore a high voltage startup cell is integrated into the ic which is switched off once the undervoltage lockout on- threshold of 15v is exceeded. the external startup resistor is no longer necessary. power losses are therefore reduced. this increases the efficiency under light load conditions dramatically. the soft-start capacitor is also used for providing an adjustable blanking window for high load jumps. during this time window the overload dete ction is disabled. with this concept no further external components are necessary to adjust the blanking window. a new latched off mode is impl emented into th e ic in order to increase the robustness and safety of the system. latched off mode is only entered if very dangerous conditions occur that damage the smps if not switched off immediately. a restart of the system can then only be done by disconnecting the ac line. auto restart mode reduces the average power conversion to a minimum. in this mode malfunctions are covered that could lead to a destruction of the smps if no dramatically reduced power limitation is pr ovided over time. once the malfunction is removed normal operation is immediately started after the next start up phase. the internal precise peak current limitation reduces the costs for the transformer and the secondary diode. the influence of the change in the input vo ltage on the power limitation can be avoided together with the integrated propagation delay compensation. therefore the maximum power is nearly independent on the input voltag e that is required for wide range smps. there is no need for an extra over sizing of the smps, e.g. the transformer or powermos. 3.2 power management figure 4 power management the undervoltage lockout monitors the external supply voltage v vcc . when the smps is plugged to the main line the internal startup cell is biased and starts to charge the external capacitor c vcc which is connected to the vcc pin. the vcc charge current that is provided by the startup cell from the hv pin is 1.05ma. when v vcc exceeds the on- threshold v ccon =15v the internal volta ge reference and bias circuit are switched on. then the startup cell is switched off by the undervoltage lockout and therefore also the power losses are switched off caused by the startup cell which is connected to the bus voltage (hv). to avoid uncontrolled ringing at switch-on a hysteresis is implemented. the switch-off of the controller can only take place after active mode was entered and v vcc falls below 8.5v. the maximum current consumption before the controller is activated is about 170 a. when v vcc falls below the off-threshold v ccoff =8.5v the internal reference is switched off and the power down reset internal bias voltage reference power management latched off mode reset v vcc < 6v 6.5v latched off mode startup cell vcc undervoltage lockout 15v 8.5v hv t1 power-down reset softs active burst mode auto restart mode
f3 ice3ds01l/lg functional description version 2.1 9 15 nov 2005 let t1 discharging the soft-start capacitor c softs at pin softs. thus it is ensured that at every startup cycle the voltage ramp at pin softs starts at zero. the internal voltage reference is switched off if latched off mode or auto restart mode is entered. the current consumption is then reduced to 300 a. when active burst mode is en tered the internal bias is switched off in order to reduce the current consumption below 1.1ma while keeping the voltage reference still active as this is necessary in this mode. in case latched off mode is entered vcc needs to be lowered below 6v to reset the latched off mode. this is done usually by disconnecting the smps from the ac line. 3.3 startup phase figure 5 soft start during the startup phase a soft start is provided. a signal v softs which is generated by the external capacitor c softs in combination with the internal pull up resistor r softs determines the duty cycle until v softs exceeds 4v. in the beginning c softs is immediately charged up to approx. 1v by t2. therefore the soft start phase takes place between 1v and 4v. above v softss = 4v there is no longer duty cycle limitation dc max is controlled by comparator c7 as comparator c2 blocks the gate g7 (see figure 6).the maximum charge current in the very first phase when v softs is below 1v is limited to 1.9ma. figure 6 startup phase by means of this extra charge stage there is no delay in the beginning of the startup phase when there is still no switching. furthermore soft start is finished at 4v to have faster the maximum power capability. the duty cycles dc 1 and dc 2 are depending on the mains and the primary inductance of the transformer. the limitation of the primary current by dc 2 is related to v softs = 4v. but dc 1 is related to a maximum primary current which is limited by the internal current limiting w ith cs = 1v. therefore the maximum startup phase is divided into a soft start phase until t1 and a phase from t1 until t2 where maximum power is provided if demanded by the fb signal. soft-start comparator soft start & g7 c7 c softs r softs t2 3.25k ? 6.5v t3 1v softs gate driver 0.85v x3.7 pwm op cs 4v c2 dc max dc 1 dc 2 t t v softs max. soft start phase 1v 4v 5.4v max. startup phase t1 t2
f3 ice3ds01l/lg functional description version 2.1 10 15 nov 2005 3.4 pwm section figure 7 pwm section 3.4.1 oscillator the oscillator generates a frequency f switch = 110khz. a resistor, a capacitor and a current source and current sink which determine the frequency are integrated. the charging and discharging current of the implemented oscillator capacitor are internally trimme d, in order to achieve a very accurate switching frequency. the ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of d max =0.72. 3.4.2 pwm-latch ff1 the oscillator clock output provides a set pulse to the pwm- latch when initiating the external power switch conduction. after setting the pwm-latch can be reset by the pwm comparator, the soft start comparator, the current-limit comparator or comparator c3. in case of resetting the driver is shut down immediately. 3.4.3 gate driver the gate driver is a fast totem pole gate drive which is designed to avoid cross conduction currents and which is equipped with a zener diode z1 (see figure 8) in order to improve the control of the gate attached power transistors as well as to protect them against undesirable gate overvoltages. the gate driver is active low at voltages below the undervoltage lockout threshold v vccoff . figure 8 gate driver the driver-stage is optimi zed to minimize emi and to provide high circuit efficiency. this is done by reducing the switch on slope when exceeding the external power switch threshold. this is achieved by a slope control of the rising edge at the driver?s output (see figure 9). figure 9 gate rising slope thus the leading switch on sp ike is minimized. when the external power switch is switched off, the falling shape of the driver is slowed down when reaching 2v to prevent an overshoot below ground. furthermore the driver circuit is designed to eliminate cross conduction of the output stage. oscillator duty cycle max gate driver 0.72 clock & g9 1 g8 pwm section ff1 r s q gate soft start comparator pwm comparator current limiting comparator c3 z1 vcc 1 pwm-latch gate t v gate 5v c load = 1nf ca. t = 130ns
f3 ice3ds01l/lg functional description version 2.1 11 15 nov 2005 3.5 current limiting figure 10 current limiting there is a cycle by cycle current limiting realized by the current-limit comparator c10 to provide an overcurrent detection. the source current of the external power switch is sensed via an external sense resistor r sense . by means of r sense the source current is transformed to a sense voltage v sense which is fed into the pin cs. if the voltage v sense exceeds the internal threshold voltage v csth the comparator c10 immediately turns off the gate drive by resetting the pwm latch ff1. a propagation delay compensation is added to support the immediate shut down without delay of the power switch in case of current limiting. the influence of the ac input voltage on the maximum output power can thereby be avoided. to prevent the current limiting from distortions caused by leading edge spikes a leading ed ge blanking is integrated in the current sense path for the comparators c10, c12 and the pwm-op. a further comparator c11 is implemented to detect dangerous current levels which could occur if there is a short winding in the transformer or the secondary diode is shorten. to ensure that there is no accidentally entering of the latched mode by the comparator c11 a spike blanking with 190ns is integrated in the ou tput path of comparator c11. the output of comparator c12 is activated by the gate g10 if active burst mode is entered. once activated the current limiting is thereby reduced to 0.257v. this voltage level determines the power level when the active burst mode is left if there is a higher power demand. 3.5.1 leading edge blanking figure 11 leading edge blanking each time when the external power switch is switched on a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. to avoid a premature termination of the switching pulse this spike is blanked out with a time constant of t leb = 220ns. during that time there can?t be an accidentally switch off of the gate drive. 3.5.2 propagation delay compensation in case of overcurrent detection the shut down of the external power switch is delayed due to the propagation delay of the circuit. this delay causes an overshoot of the peak current i peak which depends on the ratio of di/dt of the peak current (see figure 12). figure 12 current limiting the overshoot of signal2 is bigger than of signal1 due to the steeper rising waveform. this change in the slope is depending on the ac input voltage. propagation delay compensation is integrated to limit the overshoot dependency on di/dt of the rising primary current. that means the propagation delay time between exceeding the current sense threshold v csth and the switch off of the external power switch is compensated over temperature c11 current limiting c10 1.66v c12 & 0.257v leading edge blanking 220ns g10 spike blanking 190 ns propagation-delay compensation v csth active burst mode pwm latch ff1 10k ? d1 1pf pwm-op cs latched off mode t v sense v csth t leb = 220ns t i sense i limit t propagation delay i overshoot1 i peak1 signal1 signal2 i overshoot2 i peak2
f3 ice3ds01l/lg functional description version 2.1 12 15 nov 2005 within a wide range. current limiting is now possible in a very accurate way (see figure 13 ). e.g. i peak = 0.5a with r sense = 2. without propagation delay compensation the current sense threshold is set to a static voltage level v csth =1v. a current ramp of di/dt = 0.4a/s, that means dv sense /dt = 0.8v/s, and a propagation delay time of i.e. t propagation delay =180ns leads then to an i peak overshoot of 14.4%. by means of propagation delay compensation the oversh oot is only about 2% (see figure 13). figure 13 overcurrent shutdown the propagation delay compensation is realized by means of a dynamic threshold voltage v csth (see figure 14). in case of a steeper slope the switch o ff of the driver is earlier to compensate the delay. figure 14 dynamic voltage threshold v csth 3.6 control unit the control unit contains the functions for active burst mode, auto restart mode and latched off mode. the active burst mode and the auto restart mode are combined with an adjustable blanking window which is depending on the external soft start capacitor. by means of this adjustable blanking window an accident ally entering of the active burst mode is avoided. furthermore the overload detection can be deactivated for a certain time. 3.6.1 adjustable blanking window figure 15 adjustable blanking window v softs is clamped at 4.4v by the closed switch s1 after the smps is settled. if overload occurs v fb is exceeding 4.8v. auto restart mode can?t be entered as the gate g5 is still blocked by the comparator c3. but after v fb has exceeded 4.8v the switch s1 is opened via the gate g2. the external soft start capacitor can now be charged further by the integrated pull up resistor r softs . the comparator c3 releases the gates g5 and g6 once v softs has exceeded 5.4v. therefore there is no entering of auto restart mode possible during this charging time of the external capacitor c softs . the same procedure happens to the external soft start capacitor if a low load condition is detected by comparator c6 when v fb is falling below 1.32v. only after v softs has exceeded 0,9 0,95 1 1,05 1,1 1,15 1,2 1,25 1,3 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 with compensation without compensation d t dv sense s v sense v v t v csth v osc signal1 signal2 v sense propagation delay max. duty cycle off time t c3 5.4v c4 4.8v c6 1.32v & g5 & g6 4.4v s1 & g4 1 g2 control uni t 5k ? active burst mode auto restart mode r softs 6.5v softs fb
f3 ice3ds01l/lg functional description version 2.1 13 15 nov 2005 5.4v and v fb is still below 1.32v active burst mode is entered. once active burst mode is entered gate g4 is blocked to ensure that the blanking window is only active before entering the active burst mode. 3.6.2 active burst mode the controller provides active burst mode for low load conditions at v out . active burst mode increases significantly the efficiency at light load conditions while supporting a low ripple on v out and fast response on load jumps. during active burst mode which is controlled only by the fb signal the ic is always active and can therefore immediately response on fast changes at the fb signal. the startup cell is kept switched off to avoid increased power losses for the self supply. figure 16 active burst mode the active burst mode is loca ted in the control unit. figure 16 shows the related components. 3.6.2.1 entering active burst mode the fb signal is always observed by the comparator c6 if the voltage level falls below 1.32 v. in that case the switch s1 is released which a llows the capacitor c softs to be charged starting from the clamped voltage level at 4.4v in normal operating mode. the gate g11 is blocked before entering active burst mode. if v softs exceeds 5.4v the comparator c3 releases the gate g6 to enter the active burst mode. the time window that is generated by combining the fb and softs signals with gate g6 avoids a sudden entering of the active burst mode due to la rge load jumps. this time window can be adjusted by the external capacitor c softs . after entering active burst mode a burst flag is set which blocks the gate g4 and the internal bias is switched off in order to reduce the current consumption of the ic down to ca. 1.1ma. in this off state ph ase the ic is no longer self supplied so that therefore c vcc has to provide the vcc current (see figure 17). furthermore gate g11 is then released to start the next burst cycle once 1.32v is again exceeded. it has to be ensured by the ap plication that the vcc remains above the undervoltage lockout level of 8.5v to avoid that the startup cell is accident ally switched on. otherwise power losses are significantly increased. the minimum vcc level during active burst mode is depending on the load conditions and the application. the lowest vcc level is reached at no load conditions at v out . 3.6.2.2 working in active burst mode after entering the active burs t mode the fb voltage rises as v out starts to decrease due to the inactive pwm section. comparator c5 observes the fb signal if the voltage level 4v is exceeded. in that case the internal circuit is again activated by the internal bias to start with switching. as now in active burst mode the gate g10 is released the current limit is only 0.257v to reduce the conduction losses and to avoid audible noise. if the load at v out is still below the starting level for the active burst mode the fb signal decreases down to 1.32v. at this level c6 deactivates again the internal circuit by switching off the internal bias. the gate g11 is released as after entering active burst mode the burst flag is set. if workin g in active burst mode the fb voltage is changing like a saw tooth between 1.32v and 4v (see figure 17). 3.6.2.3 leaving active burst mode the fb voltage immediately increases if there is a high load jump. this is observed by comparator c4. as the current limit is ca. 26% during active burst mode a certain load jump is needed that fb can exceed 4.8v. at this time c4 resets the active burst mode which also blocks c12 by the c3 5.4v c4 4.8v c6 1.32v c5 4.0v & & g4 fb control uni t active burst mode 4.4v s1 5k ? internal bias r softs 6.5v softs g6 & g11 & g10 current limiting
f3 ice3ds01l/lg functional description version 2.1 14 15 nov 2005 gate g10. maximum current can now be provided to stabilize v out . figure 17 signals in active burst mode 3.6.3 protection modes the ic provides several protection features which are separated into two categories. some enter latched off mode, the others enter auto restart mode. the latched off mode can only be reset if vcc is falling below 6v. both modes prevent the smps from destructive states. the following table shows the relationship between possible system failures and the chosen protection modes. 3.6.3.1 latched off mode figure 18 latched off mode the vcc voltage is observed by comparator c1 if 21v is exceeded. the output of c1 is combined with the output of c4 which observes fb signal if 4.8v is exceeded. therefore the overvoltage detection is only activated if the fb signal is 1.32v 4.00v 4.80v v fb 4.40v 5.40v v softs t t 0.257v 1.00v v cs 8.5v v vcc t t 1.1ma i vcc t 7.2ma v out t max. ripple < 1% blanking window entering active burst mode leaving active burst mode current limit level during active burst mode vcc overvoltage latched off mode overtemperature latched off mode short winding/short diode latched off mode overload auto restart mode open loop auto restart mode vcc undervoltage auto restart mode short optocoupler auto restart mode c1 21v spike blanking 8.0us & g1 1 g3 thermal shutdown t j >140c latched off mode vcc c4 4.8v fb c11 1.66v spike blanking 190 ns cs voltage reference control unit latched off mode reset v vcc < 6v
f3 ice3ds01l/lg functional description version 2.1 15 15 nov 2005 outside the operating range > 4.8v, e.g. when open loop happens. therewith small voltage overshoots of v vcc during normal operating can not start the latched off mode. the internal voltage reference is switched off once latched off mode is entered in order to reduce the current consumption of the ic as much as possible. latched off mode can only be reset by decreasing v vcc < 6v. in this stage only the uvlo is working which controls the startup cell by switching on/off at v vccon /v vccoff . in this phase the average current consumption is only 300 a. as there is no longer a self supply by th e auxiliary winding vcc drops. the undervoltage lockout switches on the integrated startup cell when vcc falls below 8.5v. the startup cell is switched off again when vcc has exceeded 15v. as the latched off mode was entered there is no start up phase after vcc has exceeded the switch-on level of the undervoltage lockout. therefore vcc changes between the switch-on and switch-off levels of the undervoltage lockout with a saw tooth shape (see figure 19). figure 19 signals in latched off mode after detecting a junction temperature higher than 140c latched off mode is entered. the signals coming from the temperature detection and vcc overvoltage detection are fed into a spike blanking with a time constant of 8.0 s to ensure system reliability. furthermore short winding and short diode on the secondary side can be detected by the comparator c11 which is in parallel to the propagation delay compensated current limit comparator c10. in normal operating mode comparator c10 keeps the maximum level of the cs signal at 1v. if there is a failure such as short winding or short diode c10 is no longer able to limit the cs signal at 1v. c11 detects then the over current and enters immediately the latched off mode to keep the smps in a safe stage. 3.6.3.2 auto restart mode figure 20 auto restart mode in case of overload or open loop fb exceeds 4.8v which will be observed by c4. at this time s1 is released that v softs can increase. if v softs exceeds 5.4v which is observed by c3 auto restart mode is entered as both inputs of the gate g5 are high. in combining the fb and softs signals there is a blanking window generated which prevents the system to enter auto restart mode due to large load jumps. this time window is the same as for the active burst mode and can therefore be adjusted by the external c softs . in case of vcc undervoltage the uvlo starts a new startup cycle. short optocoupler leads to vcc undervoltage as there is now self supply after activating the internal reference and bias. in contrast to the latched off mode there is always a startup phase with switching cycles in auto restart mode. after this start up phase the conditions are again checked whether the failure is still present. normal operation is proceeded once the failure mode is removed that leads to auto restart mode. 8.5v t i vccstart t 1.05ma v out v vcc 15v c3 5.4v c4 4.8v & g5 4.4v s1 1 g2 control unit 5k ? auto restart mode r softs 6.5v softs fb voltage reference
f3 ice3ds01l/lg electrical characteristics version 2.1 16 15 nov 2005 4 electrical characteristics note: all voltages are measured with respect to ground (pin 8). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capacitor that will be connected to pin 7 (vcc) is discharged before assembling the application circuit. 4.2 operating range note: within the operating range the ic operates as described in the functional description. parameter symbol limit values unit remarks min. max. hv voltage v hv -500vv vcc supply voltage v vcc -0.3 22 v fb voltage v fb -0.3 6.5 v softs voltage v softs -0.3 6.5 v gate voltage v gate -0.3 22 v internally clamped at 11.5v cs voltage v cs -0.3 6.5 v junction temperature t j -40 150 c storage temperature t s -55 150 c total power dissipation p totdso8 - 0.45 w pg-dso-8-8, t amb < 50c p totdip8 - 0.90 w pg-dip-8-6, t amb < 50c thermal resistance junction-ambient r thjadso8 - 185 k/w pg-dso-8-8 r thjadip8 - 90 k/w pg-dip-8-6 esd capability (incl. pin hv) v esd - 3 kv human body model 1) 1) according to eia/jesd22-a114-b (discharging a 100pf capacitor through a 1.5k ? series resistor) parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc v vccoff 20 v junction temperature of controller t jcon -25 130 c max value limited due to thermal shut down of controller
f3 ice3ds01l/lg electrical characteristics version 2.1 17 15 nov 2005 4.3 characteristics 4.3.1 supply section note: the electrical characteristics involve the spread of values guaranteed wi thin the specified supply voltage and junction temperature range t j from ? 25 c to 130 c. typical values represent the median values, which are related to 25c. if not otherwis e stated, a supply voltage of v cc = 15 v is assumed. 4.3.2 internal voltage reference parameter symbol limit values unit test condition min. typ. max. start up current i vccstart - 170 220 av vcc =14v vcc charge current i vcccharge1 -1.60 -1.05 -0.55 ma v vcc = 0v i vcccharge2 --0.88-mav vcc =14v start up cell leakage current i startleak -220 av vcc >16v supply current with inactive gate i vccsup1 -6.07.5ma supply current with active gate (c load =1nf) i vccsup2 -7.28.7mav softs = 4.4v i fb = 0 supply current in latched off mode i vcclatch - 300 - ai fb = 0 i softs = 0 supply current in auto restart mode with inactive gate i vccrestart - 300 - ai fb = 0 i softs = 0 supply current in active burst mode with inactive gate i vccburst1 -1.11.3mav fb = 2.5v v softs = 4.4v i vccburst2 -1.01.2mav vcc = 9v v fb = 2.5v v softs = 4.4v vcc turn-on threshold vcc turn-off threshold vcc turn-on/off hysteresis v vccon v vccoff v vcchys 14.2 8.0 - 15.0 8.5 6.5 15.8 9.0 - v v v parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v ref 6.37 6.50 6.63 v measured at pin fb i fb = 0
f3 ice3ds01l/lg electrical characteristics version 2.1 18 15 nov 2005 4.3.3 pwm section 4.3.4 control unit note: the trend of all the voltage levels in the cont rol unit is the same regarding the deviation except v vccovp and v vccpd parameter symbol limit values unit test condition min. typ. max. fixed oscillator frequency f osc1 98 110 119 khz f osc2 102 110 117 khz t j = 25c max. duty cycle d max 0.67 0.72 0.77 min. duty cycle d min 0- - v fb < 0.3v pwm-op gain a v 3.5 3.7 3.9 max. level of voltage ramp v max-ramp -0.85-v v fb operating range min level v fbmin 0.3 0.7 - v v fb operating range max level v fbmax - - 4.75 v cs=1v limited by comparator c4 1) 1) design characteristic (not meant for production testing) feedback pull-up resistor r fb 16 20 27 k ? soft-start pull-up resistor r softs 39 50 62 k ? parameter symbol limit values unit test condition min. typ. max. deactivation level for softs comparator c7 by c2 v softsc2 3.85 4.00 4.15 v v fb > 5v clamped v softs voltage during normal operating mode v softsclmp 4.23 4.40 4.57 v v fb < 4.5v activation limit of comparator c3 v softsc3 5.20 5.40 5.60 v v fb > 5v softs startup current i softsstart -1.9-mav softs = 0v active burst mode level for comparator c6 v fbc6 1.23 1.32 1.40 v v softs > 5.6v active burst mode level for comparator c5 v fbc5 3.85 4.00 4.15 v after active burst mode is entered over load & open loop detection limit for comparator c4 v fbc4 4.62 4.80 4.98 v v softs > 5.6v overvoltage detection limit v vccovp 20 21 22 v v fb > 5v latched thermal shutdown t jsd 130 140 150 c guaranteed by design spike blanking t spike -8.0- s power down reset for latched mode v vccpd 4.0 6.0 7.5 v after latched off mode is entered
f3 ice3ds01l/lg electrical characteristics version 2.1 19 15 nov 2005 4.3.5 current limiting 4.3.6 driver section parameter symbol limit va lues unit test condition min. typ. max. peak current limitation (incl. propagation delay time) (see figure 7) v csth 0.950 1.000 1.050 v dv sense / dt = 0.6v/ s over current detection for latched off mode v cs1 1.570 1.66 1.764 v peak current limitation during active burst mode v cs2 0.232 0.257 0.282 v v fb < 1.2v leading edge blanking t leb -220-nsv softs = 4.4v cs spike blanking for comparator c11 t csspike -190-ns cs input bias current i csbias -1.0 -0.2 0 av cs =0v parameter symbol limit values unit test condition min. typ. max. gate low voltage v gatelow --1.2vv vcc = 5 v i gate = 5 ma --1.5vv vcc = 5 v i gate = 20 ma -0.8-vi gate = 0 a -1.62.0vi gate = 20 ma -0.2 0.2 - v i gate = -20 ma gate high voltage v gatehigh - 11.5 - v v vcc = 20v c l = 4.7nf - 10.5 - v v vcc = 11v c l = 4.7nf -7.5-vv vcc = v vccoff + 0.2v c l = 4.7nf gate rise time (incl. gate rising slope) t rise - 150 - ns v gate = 2v ...9v 1) c l = 4.7nf 1) transient reference value gate fall time t fall -55-nsv gate = 9v ...2v 1) c l = 4.7nf gate current, peak, rising edge i gate -0.5 - - a c l = 4.7nf 2) 2) design characteristic (not meant for production testing) gate current, peak, falling edge i gate --0.7ac l = 4.7nf 2)
version 2.1 20 15 nov 2005 f3 ice3ds01l/lg typical performance characteristics 5 typical performance characteristics figure 21 start up current i vccstart figure 22 vcc charge current i vcccharge1 figure 23 vcc charge current i vcccharge2 figure 24 vcc supply current i vccsup1 figure 25 vcc supply current i vccsup2 figure 26 vcc supply current i vcclatch junction temperature [c] start up current i vccstart [ua] pi-001 150 154 158 162 166 170 174 178 182 186 190 -25-15-5 5 152535455565758595105115125 junction temperature [c] vcc charge current i vcccharge1 [ma] pi-002 0,5 0,6 0,7 0,8 0,9 1,0 1,1 1,2 1,3 1,4 1,5 -25-15-5 5 152535455565758595105115125 junction temperature [c] vcc charge current i vcccharge2 [ma] pi-003 0,5 0,6 0,7 0,8 0,9 1,0 1,1 1,2 1,3 1,4 1,5 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] vcc supply current i vccsup1 [ma] pi-004 3,0 3,5 4,0 4,5 5,0 5,5 6,0 6,5 7,0 7,5 8,0 -25-15-5 5 152535455565758595105115125 junction temperature [c] vcc supply current i vccsup2 [ma] pi-005 4,0 4,5 5,0 5,5 6,0 6,5 7,0 7,5 8,0 8,5 9,0 -25-15-5 5 152535455565758595105115125 junction temperature [c] vcc supply current i vcclatch [ua] pi-006 200 220 240 260 280 300 320 340 360 380 400 -25-15-5 5 152535455565758595105115125
f3 ice3ds01l/lg typical performance characteristics version 2.1 21 15 nov 2005 figure 27 vcc supply current i vccrestart figure 28 vcc supply current i vccburst1 figure 29 vcc supply current i vccburst2 figure 30 vcc turn-on threshold v vccon figure 31 vcc turn-off threshold v vccoff figure 32 vcc turn-on/off hysteresis v vcchys junction temperature [c] vcc supply current i vccrestart [ua] pi-007 200 220 240 260 280 300 320 340 360 380 400 -25-15-5 5 152535455565758595105115125 junction temperature [c] vcc supply current i vccburst1 [ma] pi-008 0,90 0,93 0,96 0,99 1,02 1,05 1,08 1,11 1,14 1,17 1,20 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] vcc supply current i vccburst2 [ma] pi-009 0,90 0,93 0,96 0,99 1,02 1,05 1,08 1,11 1,14 1,17 1,20 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] vcc turn-on threshold v vccon [v] pi-010 14,0 14,2 14,4 14,6 14,8 15,0 15,2 15,4 15,6 15,8 16,0 -25-15-5 5 152535455565758595105115125 junction temperature [c] vcc turn-off threshold v vccoff [v] pi-011 8,0 8,1 8,2 8,3 8,4 8,5 8,6 8,7 8,8 8,9 9,0 -25-15-5 5 152535455565758595105115125 junction temperature [c] vcc turn-on/off hysteresis v vcchys [v] pi-012 6,0 6,1 6,2 6,3 6,4 6,5 6,6 6,7 6,8 6,9 7,0 -25-15-5 5 152535455565758595105115125
f3 ice3ds01l/lg typical performance characteristics version 2.1 22 15 nov 2005 figure 33 reference voltage v ref figure 34 oscillator frequency f osc1 figure 35 max. duty cycle d max figure 36 pwm-op gain a v figure 37 max. level voltage ramp v max-ramp figure 38 feedback pull-up resistor r fb junction temperature [c] reference voltage v ref [v] pi-013 6,40 6,42 6,44 6,46 6,48 6,50 6,52 6,54 6,56 6,58 6,60 -25-15-5 5 152535455565758595105115125 junction temperature [c] oscillator frequency f osc1 [khz] pi-014 100 102 104 106 108 110 112 114 116 118 120 -25-15-5 5 152535455565758595105115125 junction temperature [c] max. duty cycle pi-015 0,700 0,705 0,710 0,715 0,720 0,725 0,730 0,735 0,740 0,745 0,750 -25-15-5 5 152535455565758595105115125 junction temperature [c] pwm-op gain a v pi-016 3,50 3,54 3,58 3,62 3,66 3,70 3,74 3,78 3,82 3,86 3,90 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] max. level voltage ramp v max-ramp [v] pi-017 0,60 0,65 0,70 0,75 0,80 0,85 0,90 0,95 1,00 1,05 1,10 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] feedback pull-up resistor r fb [kohm] pi-018 16 17 18 19 20 21 22 23 24 25 26 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
f3 ice3ds01l/lg typical performance characteristics version 2.1 23 15 nov 2005 figure 39 soft-start pull-up resistor r softs figure 40 threshold comparator c2 v softsc2 figure 41 clamped softs voltage v softsclmp figure 42 threshold comparator c3 v softsc3 figure 43 threshold comparator c6 v fbc6 figure 44 threshold comparator c5 v fbc5 junction temperature [c] soft-start pull-up resistor r softs [kohm] pi-019 40 42 44 46 48 50 52 54 56 58 60 -25-15-5 5 152535455565758595105115125 junction temperature [c] threshold comparator c2 v softsc2 [v] pi-020 3,80 3,84 3,88 3,92 3,96 4,00 4,04 4,08 4,12 4,16 4,20 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] clamped softs voltage v softsclmp [v] pi-021 4,20 4,24 4,28 4,32 4,36 4,40 4,44 4,48 4,52 4,56 4,60 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] threshold comparator c3 v softsc3 [v] pi-022 5,15 5,20 5,25 5,30 5,35 5,40 5,45 5,50 5,55 5,60 5,65 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] threshold comparator c6 v fbc6 [v] pi-023 1,280 1,288 1,296 1,304 1,312 1,320 1,328 1,336 1,344 1,352 1,360 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] threshold comparator c5 v fbc5 [v] pi-024 3,80 3,84 3,88 3,92 3,96 4,00 4,04 4,08 4,12 4,16 4,20 -25-15-5 5 152535455565758595105115125
f3 ice3ds01l/lg typical performance characteristics version 2.1 24 15 nov 2005 figure 45 threshold comparator c4 v fbc4 figure 46 overvoltage detection limit v vccovp figure 47 threshold power down reset v vccpd figure 48 peak current limitation v csth figure 49 over current detection v cs1 figure 50 peak current limitation v cs2 junction temperature [c] threshold comparator c4 v fbc4 [v] pi-025 4,60 4,64 4,68 4,72 4,76 4,80 4,84 4,88 4,92 4,96 5,00 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] overvoltage detection limit v vccovp [v] pi-026 20,0 20,2 20,4 20,6 20,8 21,0 21,2 21,4 21,6 21,8 22,0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] vcc power down reset v vccpd [v] pi-027 4,0 4,4 4,8 5,2 5,6 6,0 6,4 6,8 7,2 7,6 8,0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] peak current limitation v csth [v] pi-028 0,95 0,96 0,97 0,98 0,99 1,00 1,01 1,02 1,03 1,04 1,05 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] over current detection v cs1 [v] pi-029 1,580 1,592 1,604 1,616 1,628 1,640 1,652 1,664 1,676 1,688 1,700 -25-15-5 5 152535455565758595105115125 junction temperature [c] peak current limitation v cs2 [v] pi-030 0,240 0,243 0,246 0,249 0,252 0,255 0,258 0,261 0,264 0,267 0,270 -25-15-5 5 152535455565758595105115125
f3 ice3ds01l/lg typical performance characteristics version 2.1 25 15 nov 2005 figure 51 leading edge blanking t leb figure 52 cs spike blanking for c11 t csspike figure 53 gate low voltage v gatelow figure 54 gate high voltage v gatehigh figure 55 gate rise time t rise figure 56 gate fall time t fall junction temperature [c] leading edge blanking t leb [ns] pi-031 100 130 160 190 220 250 280 310 340 370 400 -25-15-5 5 152535455565758595105115125 junction temperature [c] cs spike blanking for c11 t csspike [ns] pi-032 100 120 140 160 180 200 220 240 260 280 300 -25-15-5 5 152535455565758595105115125 junction temperature [c] gate low voltage v gatelow [v] pi-033 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1,0 1,1 1,2 1,3 -25-15-5 5 152535455565758595105115125 junction temperature [c] gate high voltage v gatehigh [v] pi-034 9,0 9,3 9,6 9,9 10,2 10,5 10,8 11,1 11,4 11,7 12,0 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 junction temperature [c] gate rise time t rise [ns] pi-035 100 120 140 160 180 200 220 240 260 280 300 -25-15-5 5 152535455565758595105115125 junction temperature [c] gate fall time t fall [ns] pi-036 40 44 48 52 56 60 64 68 72 76 80 -25-15-5 5 152535455565758595105115125
f3 ice3ds01l/lg outline dimension version 2.1 26 15 nov 2005 6 outline dimension figure 57 figure 58 dimensions in mm pg-dip-8-6 (plastic dual in-line outline) pg-dso-8-8 (plastic dual small outline)
qualit?t hat fr uns eine umfassende bedeutung. wir wollen allen ihren ansprchen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstrengungen gelten gleicherma?en der lieferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total quality im denken und handeln gegenber kollegen, lieferanten und ihnen, unserem kunden. unsere leitlinie ist jede aufgabe mit ?null fehlern? zu l?sen ? in offener sichtweise auch ber den eigenen arbeitsplatz hinaus ? und uns st?ndig zu verbessern. unternehmensweit orientieren wir uns dabei auch an ?top? (time optimized processes), um ihnen durch gr??ere schnelligkeit den entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns die chance, hohe leistung durch umfassende qualit?t zu beweisen. wir werden sie berzeugen. quality takes on an allencompassing significance at semiconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total quality in thought and deed, towards co-workers, suppliers and you, our customer. our guideline is ?do everything with zero defects?, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), greater speed on our part to give you that decisive competitive edge. give us the chance to prove the best of performance through the best of quality ? you will be convinced. http://www.infineon.com total quality management published by infineon technologies ag

▲Up To Search▲

Price & Availability of ICE3DS01L05

	To Download ICE3DS01L05 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .